Advanced Techniques Of DFT Simulation

Abstract

As we know that fabrication process of chip is not 100% defect free so testing ofchip is required.To make chip Testable we add controllability and observability at each and every node.

To make digital circuit’s internal lode testable we need to replace each storage element with scan cell.each scan-cell has two input.Thatcan be selected.The first input is the data input which is driven by the combinational logic of a circuit, and the second input which is scan input which is driven by the output of another scan cell in order to form one or more shift registers called scan chains.scan chains can be made externally accessible(from top level in-out) by connecting the scan input of the first scan cell in a scan chain to a primary input and the output of the last scan cell in a scan chain to the primary output.Test generation is the task of producing a set of test vectors(pattern) that will uncover any defect in a chip.This pattern are used at tester.so my project is to validate that patterns.To validate test pattern simulate pattern generated by ATPG.Different techniques is used for simulation.I have used different commands to detect glitches,for parallel simulation(which reduced simulation time),for detection of race condition.For Timing Simulation SDF file is required which back annotate delay.If pattern failure then by tracing chain and by dumpingvariable find reason for failure.