Advanced Routing Algorithm for FUB Integration

Abstract

VLSI refers to a technology through which it is possible to implement large circuits in silicon circuits with up to a million transistors. The VLSI technology has been successfully used to build microprocessors, signal processors, systolic arrays, large capacity memories, memory controllers and interconnection networks. Chip designing consists of various design processes like architectural design, logic design, circuit design, physical design, physical verification and signoff, fabrication, packaging and testing etc. Physical design is one of the important phase of VLSI design cycle. Continuous shift towards the design in nanometer scale has been increasing complexity in physical designing of the chip. It introduces new metal layers and DRC runsets which increases complexity of the layout. In Full chip designs, as the chip area is reduced with increased feature requirement the complexity of the interconnect design increases with great extent. On the other hand, it is important to save on interconnection cost ,since wires are far more expensive in VLSI than transistors. Among these design issues, rising RC delay on on-chip wiring, increasing noise susceptibility due to coupling, delay prediction considering inductance and noise effects, and power and reliability concerns due to increasing current density are commonly mentioned. The gap between device and wire delays is increased, especially the global interconnect delays, which do not scale well with the feature size. Interconnect routing directly impacts circuit performance, area, reliability, power, and manufacturing yield .Optimization of interconnect routing is required to achieve high performance. Full chip interconnect routing is done in three steps; global routing, timing driven routing and detailed routing. In a complex VLSI chip, interconnect routing free of DRC and LVS violation is also essential to get better power and noise performance. In this report, detailed routing is discussed. In the process of automatic design of VLSI layouts, routing is accomplished using computer programs called routers. In this report, QEA router and problems associated with the QEA router are discussed. To overcome all those problems and increase efficiency, advanced routing algorithm for FUB integration is developed and enhanced in different ways. Result shows that it is successful in saving time as well as effort. With the help of advanced routing algorithm for FUB integration, routing quality is improved and design cycle time is reduced.