Development of Advance ATPG Using Probabilistic Approach

Abstract

To Test the functioning of IC in today's era, Automatic Test Pattern Generator (ATPG) is becoming very important as circuit become more & more complicated. Fault coverage should be high to detect maximum faults in design, while maintaining design overhead with in certain limit. Design reliability should be high with minimum cost and time. ATPG is beneficial in many ways. First, it can reduce the test time for a large circuit. In addition, ATPG can provide at speed testing. Stuck at fault model is considered throughout this project. Considering stuck at fault, the fault list becomes lengthy as circuit size increases. Fault Equivalence method is used to reduce fault in the circuit. Testability measures like controllability and Observability are considered to find how complicated is to test internal nodes. Controllability uses to guides the test generation algorithms while setting a value of net in line justification problem. To generate test vector for any fault involves "line activation", "Fault Propagation", and "line justification" step. The EDA Tool is developed using C Programming language for 3 fan-in. Developed ATPG Tool is generic and can be used for any combinational logic Circuit. An efficient and simple technique used for test pattern generation is necessary with the intention of reducing number of faults. This algorithm must be simple. In this project combinational ATPG is developed based on testability measures, And Probability is used for finding fault which is hardest to and. So using Probability, Undetectable Faults are found early in Test Pattern Generation so we do not have to scan all Fault list.