Power Reduction Evaluation of High Speed Cores Including Automation for P&R Productivity Enhancement

Abstract

With time, in present and upcoming era of VLSI, technology is moving at speed of light. The world is demanding the gadgets with a compact size and a high speed performance. Further going down to the technology the design tries to achieve the speed, but along with which comes a severe problem of POWER. As the technology goes on shrinking there comes a problem with leakage power and as a result of which there comes a heating problem which leads to EM effects in the design. Hence, it becomes a very important role for a design engineer to take a very important prevention of leakage and power dissipation. As a result of which an engineer goes for a low power reduction techniques, i.e. a low power or low energy consumption technology design. The major design parameters of a VLSI design are power, area and operating frequency.Here in this Report, we will be discussinghow low power design can be made using different low power techniques in the current PnR implementation flow methodology, along with the modern PnR implementation flow methodology to achieve the optimized design with required tradeoffs. The flow for design implementation and power number analysis is automated using scripts written in TCL, while VCD, switching activity file extraction flow is to carried out manually, which is used for getting the accurate power numbers of the design, average power numbers(at front-end side) and peak power numbers(at back-end side).