DFT Verification and Pattern Simulation for Analog IP

Abstract

Nowadays, System-on-chip (SoC) becomes more complex. SoC have large number of core and various IP. Physical dimension of devices are also deceasing as well. Due to smaller dimension it is difficult to access the test point. Here DFT techniques come to picture. Increasing coverage (Access all components of SoC in stand- alone mode or functional mode) and decreasing test cost is very emerging topic in research areas. Adding extra module DFT module in SoC also requires conventional verification. DFT module increase complexity of SoC but it help to generate specific test vector which helps reducing test pattern ultimate reducing the chip cost. There are various DFT techniques like BIST, MBIST and scan chain insertion. Here we seen how to test the standalone analog IP through TCU and pattern simulation for various fault model.