Fault Analysis of QCA Combinational Circuit at Layout & Logic Level

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DC Field	Value	Language
dc.contributor.author	Dhare, Vaishali	-
dc.contributor.author	Mehta, Usha	-
dc.date.accessioned	2017-01-24T07:46:22Z	-
dc.date.available	2017-01-24T07:46:22Z	-
dc.date.issued	2015-12-19	-
dc.identifier.citation	International WIE Conference on Electrical and Computer Engineering (WIECON - ECE), BUET, Dhaka, Bangladesh, December 19 - 20, 2015, Page No. 22 - 26	en_US
dc.identifier.issn	978-1-4673-8786-6/15	-
dc.identifier.uri	http://hdl.handle.net/123456789/7335	-
dc.description.abstract	QCA (Quantum-dot Cellular Automata) is the most capable future nanotechnology for computing. Defects are most likely to occur in QCA devices due to the nanoscale. Faults caused by these defects must be analyzed. This paper implement the QCA combinational circuit, half adder for which fault analysis is carried out. This paper presents the fault analysis of QCA combinational circuit, half adder at layout level using QCADesigner tool and at logic level using Hardware description Language for QCA (HDLQ).	en_US
dc.relation.ispartofseries	ITFEC022-10;	-
dc.subject	Quantum-Dot	en_US
dc.subject	QCA	en_US
dc.subject	Defect	en_US
dc.subject	HDLQ	en_US
dc.subject	EC Faculty Paper	en_US
dc.subject	Faculty Paper	en_US
dc.subject	ITFEC022	en_US
dc.subject	ITFEC010	en_US
dc.title	Fault Analysis of QCA Combinational Circuit at Layout & Logic Level	en_US
dc.type	Faculty Papers	en_US
Appears in Collections:	Faculty Papers, EC

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