Investigations on Generalization of Current Error Space Phasor Based Pulse Width Modulation Controller for Multi-Level Front-End Converters

Abstract

Three-phase ac-dc converters are integral part of many industrial applications. Diode and thyristor based rectifiers are classical examples of unidirectional non-linear loads. To mitigate the current harmonics generated by these rectifiers, and to improve the quality of power, passive and/or active power filters are suggested in literature. Filters provide costly solution for power quality improvement by demanding additional hardware. Hence, it is always preferred to produce the converter which do not create such issues. Multi-pulse rectifiers are used for power quality improvement in high-power applications, but they require phase shifting transformers which make system bulky and costly. IGBT based multi-level converters are used as front-end topology for high-power applications with bi-directional power flow capability. Most of the high-performance converters employ current controlled pulse width modulation techniques for fast dynamic response and inherent protection against overcurrents. Selection of current control strategy is very crucial in the case of front-end converter (FEC), as it directly affects the performance of converter in terms of improvement in harmonic profile of source current and obtaining unity power factor at supply side in association with good dynamic response. Current error space phasor based hysteresis controller (CESP based HC) is proposed in this thesis. The controller deals with current error space phasor, which signifies the combined effect of the current errors in the individual phases. It monitors the movement of CESP and enables the use of zero voltage vector along with active voltage vectors of FEC. The controller allows switching of only adjacent voltage vectors in a given sector of voltage space phasor structure of FEC, which eliminates the selection of random voltage vectors, as observed with conventional hysteresis controller. The proposed controller ensures effective tracking of actual current with reference current by continuously restricting the current error space phasor movement within the prescribed hexagonal boundary. The voltage space phasor structure of two-level FEC has six triangular sectors. In the proposed work, sector detection logic is developed by sensing and comparing the instantaneous value of three-phase supply voltages for two-level FEC. The CESP based HC with single hysteresis band is applied and analyzed for two-level front-end converter. The proposed controller is able to give unity power factor and low %THD (less than allowable limit of standard IEEE-519-2014) with good line as well as load regulations, as evident from presented simulation and experimental results. However, as one moves from two-level to multi-level converters (more than two-level), voltage space phasor structure of FEC becomes more complex with increased number of sectors. Proposed logic of sector detection for two-level FEC with single hysteresis band cannot be directly extended to multi-level FECs. Hence, another band, called outer hysteresis band, is introduced in the proposed CESP based HC for sector changeover detection, involving inner and outer hysteresis bands for detecting necessary region of boundary (for selection of voltage vector) and sector change according to the position of reference voltage vector, respectively. During each sector change, the CESP moves out of the inner hexagonal boundary to hit the outer hysteresis band (six times, eighteen times and forty two times in one fundamental cycle of supply voltage for two-level, three-level and five-level, converter respectively). This puts serious limitation on the improvement of harmonic spectrum of the supply current and increases the complexity in real-time implementation. Proposed CESP based HC with two hysteresis bands is applied to two-level and three-level flying capacitor front-end converters, with capacitor voltage balancing scheme for three-level FEC. Proposed capacitor voltage balancing scheme effectively uses the redundancy of switching states offered by flying capacitor (FC) topology to balance the capacitor voltages. From the presented results, it is confirmed that current error space phasor moves many times out of inner hexagonal boundary in a fundamental cycle to detect the sector changeover, and in-turn distorts the input current waveform (increases %THD of line current). A fractal approach based technique is proposed in this thesis to eliminate outer hysteresis band and limit current error space phasor within the hexagonal boundary during sector changeover also for any general n-level multi-level FEC. In present work, CESP based HC controller employing fractal approach is applied to three-level FC topology and results are presented for various steady state and dynamic conditions to validate the performance of proposed controller in terms of unity power factor at line side, constant output dc-link voltage at load side, and bi-directional power flow capability. It also improves the harmonic profile of line current. The controller automatically takes the front-end converter into overmodualtion at times of contingency to satisfy the load demand and brings back to normal mode of operation, once the contingency is over. This proves the self-adaptive nature of the proposed controller. A flowchart is developed for the proposed fractal approach making it possible to detect sector for any general n-level multi-level converter. The proposed scheme is general in nature and can be very easily extended for any n-level multi-level front-end converter. All the proposed solutions are implemented using real time simulator hardware-in-loop system (OPAL-RT 4510) under rapid control prototyping mode. Presented experimental results are found in close resemblance with the results obtained in simulation studies for all steady state and dynamic conditions of the two-level and three-level FC FECs.