Power Modelling and Analysis of Mobile Chip

Abstract

VLSI industries are moving to low power designs due to high demand of mobile devices. So to design a compact gadget, one of the key parameters is to reduce power consumption. This thesis explains the Intel power modelling methodology for power estimation which is used to find power dissipation for different partitions on a design at different levels of hierarchy. In this thesis the analysis of power reports includes estimation of major power consuming area of SoC, the scope of its power reduction and evaluating the performance which helps to build a power efficient design. In SoC there is one important partition Graphics Processing Unit (GPU), which is explained in detail and its dynamic, leakage and total power values have been analyzed with the help of PTPX tool. GPU’s power is reduced by implementing End to End graphics compression with the help of power modelling. In this thesis the other two techniques also used for reducing Graphics memory bandwidth. One is Hardware Composition and another is Texture Compression. These techniques have their own limitations, which is also explained in this thesis. Modern GPUs are capable of working with the compressed data sets, which are stored in memory and they can be operated without decompressing the data on throughout the pipeline. At last these data sets will be decompressed by display. This End to End graphics compression is now implemented for mobile SoC. It reduces GPU power by 15-20% and Graphics memory bandwidth by 30-33%. It is totally dependent on the type of workload for which GPU will be used.