How to Validate Machine Check Architecture Complete Flow at Full Chip Level

Abstract

As technology node shrinking number of transistors used in Processor, and faster caches memory and buses has increased the probability of data corruption due to high frequency signal transient and permanent faults. Trend going toward Cloud computing and computing clusters makes each compute node a component of a larger infrastructure. This in turn increases possibility of runtime errors and reduces the effective mean time between machine checks in the system. That why, it is critical to provide rapid identification of error symptoms which trigger corrective actions that can prevent a major entire system or application failure that part is Machine Check Architecture. Machine Check Architecture (MCA) is a processor internal mechanism that detects error symptoms and logs correctable, uncorrectable and catastrophic errors in the data or bus paths in each CPU core and the Northbridge side. Those errors include parity errors, ECC and TLBs error associated with system bus, caches memory and DRAM. In this thesis we cover between simulation and emulation which best methodology use for MCA validation and why Full Chip (FC) flow is best way for MCA complete flow validation. How we can write Test cases for MCA so it give maximum coverage and using that test case we can validate MCA complete flow. At emulation level error like catastrophic generation is critical so using existing environment how we can generate that kind of error. Write checker scripts in such a way so using that we can automate MCA validation.