Novel Physical Design Methodology for Efficient Power Optimization in SoC’s Server Partitions

Abstract

In System-on-Chips (SoCs), the most critical design constraint used to be Area and Performance but Power has also become an important constraint in recent times. Therefore, the power-aware design should be introduced in Physical Design at early stages of SoCs Server Partition where it has the highest benefits for power reduction. To make the design power-aware, new low power techniques and standards are introduced. Introduction of Unified Power Format and implementation of low power techniques in Electronic Design Automation tools has helped the designers to provide power intent separated from the design functionality during initial stages of ASIC Physical Design flow, thus reducing the power dissipation. Implementation of Multisource CTS and Multibit Flip Flop technique in SoC’s partitions reduces power consumption of design significantly. This project concludes that by implementing low power techniques using Unified Power Format, Multisource CTS and Multibit Flip Flop it is possible to make the design power aware which consumes less power.