Layout Design Of Memory and Standard Cells in 65nm Technology

Abstract

The layout phase is most critical in the design of integrated circuits (IC’s) because of the cost of the phase itself, since it involves expensive tools and a large amount of human intervention, and also because of the consequences for production cost. Several approaches are used that need more or less computer and/or man time. The compromise is difficult because of the number of parameters to be taken into account. As the device size shrinks to nanometer scale and the integration level exceeds well over giga scale, the landscape of technology developments has become very different from the past. The variability, for example, becomes a critical issue not only for performance, but also for production yield. The problems, which have been seen as secondary for long time, suddenly come into play and will grow according to the device size reduction. The solution is DFM, Design for Manufacturing. The DFM will not be done without collaborations between various technology parties, such as process, design, mask, EDA, and so on. The DFM will give us a big challenge and opportunity in nanometer era.