Verification Of IP for Clock Domain Crossing

Abstract

Today, in the era of Multi-million gate ASICs, Reusable Intellectual Property (IP), and System on Chip (SoC) designs, Verification consumes about 70% of the design effort. The number of verification engineers is usually twice the number of design engineers. When design projects are completed, the code that implements the test benches makes up to 80% of the total code volume. Verification of design is done at various levels of design phase. Shrinking device sizes and increasing complexity have created multi-million transistor systems running with multiple asynchronous clocks with frequencies as high as multiple GHz. Modern SoC designs commonly use multiple, asynchronous clocks. This can be due to interfacing different external systems, such as a SoC communicating with PCI and USB; it may also be due to chip size being too large for a single fast clock to be effectively distributed over the entire die. Even to remove clock skew problem from large chips we need multiple clocks. These asynchronous clocks create multiple clock domains in the design. When signals passes from one clock domain to another clock domain, there is a probability of occurrence of Metastability, loss of data or loss of correlation between them. So we need to verify each clock domain crossing signals for proper synchronization and stability. Chapter 1 introduces Complete CDC Verification Methodology applicable to all IPs. Chapter 2 describes problems due to CDC and their possible solutions. Chapter 3 explains use of various synchronizers for synchronizing CDC signals including special synchronizers like FIFO and Handshake. Chapter 4 introduces Assertion based verification for implementing functional checks on IPs. Appendix A explains complete flow for verification of IP using Conformal tool from Cadence. It shows implementation of different CDC checks using Conformal and its result analysis. While Appendix B contains design codes for different Synchronizers.