High Speed CMOS Transmitter Design

Abstract

The increasing processing speed of microprocessor motherboards, optical transmission links, intelligent hubs and routers, etc., is pushing the off-chip data rate into the gigabits-per-second range. However, unlike internal clocks, chip-to-board signaling gains little benefit in terms of operating frequency from the increased silicon integration. In the past, high data rates were achieved by massive parallelism, with the disadvantages of increased complexity and cost for the IC package. For this reason, the off-chip data rate should move to the range of Gb/s-per-pin. The increasing demand for the data bandwidth has driven the development of high-speed and low-cost serial link technology. In order minimize the cost of communication devices; this project develops transmitter circuit designed in 65 nm technology. The objective of this project is to realize 1Gbps serial link using CMOS technology. The major emphasis is on PLL, serializer and differential signaling for data transmission. High speed parallel to serial data conversion is achieved by means of timedivision multiplexer toggled by a low jitter clock provided by phase-locked loop.