Pre-Emphasis and Receiver Equalization

Abstract

The increasing processing speed of microprocessor motherboards, optical transmission links, intelligent hubs and routers, etc., is pushing the off-chip data rate into the gigabits-per-second range. However, unlike internal clocks, chip-to-board signaling gains little benefit in terms of operating frequency from the increased silicon integration. In the past, high data rates were achieved by massive parallelism, with the disadvantages of increased complexity and cost for the IC package. For this reason, the off-chip data rate should move to the range of Gb/s-per-pin. The increasing demand for the data bandwidth has driven the development of high-speed and low-cost serial link technology. In order to lower the cost of communication devices, this project develops equalization circuit design in 0.065μm technology using TSMC process. The objective of this project is to realize 8Gbps data rate in 16 inch no connector model. Equalization circuit can be implemented at transmitter side or receiver side. Transmitter side has disadvantage of high power consumption and receiver side disadvantage is not work proper when signal to noise ratio is main concern. So in between approach is to design equalization circuit at the both end. At transmitter side it is called Pre-Emphasis and it is designed in 65nm CMOS technology with 500mv differential output with equalization up to 13db. Receiver side Continuous Time Linear Equalization (CTLE) is implemented. There is 2-stage CTLE is implemented in 65nm CMOS technology with 500mv differential input and peaking gain is 10 DB and Eye opening of 600mv.