System Verilog Based Verification Of Digital IPs

Abstract

In order to handle the ever increasing complexity of system on- chips (SoCs) and time-to-market pressures, the design abstraction has been raised to the system level in order to increase design productivity. This higher level of abstraction generated large interest in transaction-level modeling, synthesis, and verification. Transaction based verification uses the concept of transactions to raise the verification effort to a higher level of abstraction for the purpose of improved productivity. It fundamentally relies on separating a test bench into two layers The top layer is the tests, which provide transaction level activity in the system without regard to the specific detail of signal-level protocols on the design's interfaces. The bottom layer is the transaction verification model (TVM), which provides the mapping between transaction level requests made by the tests and detailed signal-level protocols on the design's interfaces. This method makes the functional verification of IP Core more effective and it is easy to create and reuse of test benches. In today’s era System Verilog becoming more and more popular for hardware designing as well as verification purpose also because of its some magnificent features like object oriented programming, randomization, coverage analysis ability. Skye Blue Bus is developed by Freescale Semiconductor Inc. and is used in small IPs. Here to verify this bus I have used transaction based verification methodology. Using SVBCL class library I have created driver or transactor in system verilog, which generates the bus signals according to bus protocol.