Development and Implementation Of IP Core Of PSK Modulator

Abstract

Digital Modulation techniques are essential to many digital communication systems, whether it is a telephone system, a mobile cellular communication system, or a satellite communication system. The demand for a high bit rate data transmission in space applications has been rapidly increasing specially where one deals with earth observing missions. Several modulation techniques for digital transmission have recently been investigated for the purpose of achieving narrow signal spectra with power concentrated within a given bandwidth. While designing a communication system, particularly a satellite communication system, special attention is needed to use the primary resources viz., the transmitted power and channel bandwidth. Space communication links is power limited. Phase Shift Keying (PSK) modulation scheme is best suited for satellite communication since power required is optimum. The main objective of this project is to develope and implement IP Core of PSK Modulator on FPGA. This project work covers all the design and implementation details of the BPSK and QPSK Modulator. Commercial off-the-shelf (COTS) modules are used for practical study and analysis of BPSK/QPSK Modulation. The MATLAB modeling of BPSK and QPSK Modulator is performed to help the VHDL part design. The Register Transfer Level (RTL) Design of the PSK Modulator is performed using VHDL. Test Bench is developed to simulate the IP Core. The simulation result of BPSK and QPSK Modulator using MATLAB Simulink Tool Box, MATLAB coding and VHDL coding are analysis and discussed. This IP Core is implemented on XCV1000bg-6 Virtex FPGA. In addition, simulation results of VHDL Model are compared with output captured on Chipscope and Logic analyzer.