Design and Simulation of Decision Feedback Equalizer for High Speed Data Communication Using 65nm Technology

Abstract

High-speed serial interfaces, which significantly reduce I/O pin count and increase maximum bandwidth per pin, replace conventional low-speed parallel bus for backplane communications. Inter-symbol interface (ISI) is the major factor limiting the maximum transmission distance and the data rate of backplane data transmission. ISI is caused by channel impairments such as amplitude attenuation and group delay distortion. Decision feedback equalization (DFE) is one of the most effective approaches to eliminate the ISI by using past symbols interfering with the currently transmitted symbol. The usage of a DFE for signal conditioning was first suggested by Austin. In a pipelined DFE receiver with full-rate clock timing was designed and operated at 1.2Gbps. In this thesis work, Main aim is to design a pipelined DFE with 2 post-tap finite impulse responses (FIR) filter operating at half rate clock timing for data rate up to 5 Gbps. This 2 post-tap DFE receiver will be implementing in 65nm CMOS technology demonstrates max. data rate of 5 Gbps operation over a 16” FR4 backplane for a circuit. The 2 post-tap decision feedback equalizer (DFE) implementation consists of two equalizing amplifiers (summing nodes) connected to incoming data and feedback loops. Two parallel branches consisting of equalizing amplifier and two flip-flops each are also present and followed by a MUX. Also want to verify the performance of the half rate DFE by varying the temperature with different skew corner.