Functional Verification of Capture Memory Subsystem at Module Level

Abstract

As gate counts and system complexity growing exponentially, engineers confront the most perplexing challenge in chip design cycle Verification. Verification of the design RTL is done at various phases of the chip design flow at different abstraction levels. The Major Project traverses through the chip design flow and functionally verifies the module of the chip. This is done at low abstraction level concentrating on the core functionality of the module. The inputs to module are forced through the testbench and its interfaces are not looked upon. This is the verification of chip at module level and is done at the RTL design phase. The designer updates the RTL as per the feedback. After the RTL is been finalized after fixing all the bugs, it is send to the fabrication unit This project is mainly concern with the verification of the FPGA. This FPGA is used in the High Speed Memory chip tester. For verify this FPGA we used the SCIF (System C Interface) method. My area is mainly concern on the Pin-CMEM one of the block of FPGA. Writing the test case in C-side and V-side is providing the timing related information to the DUT. After applying the testcase DUT will generate the response as per the testcase configuration. This response is again passing through v-side and compare with the expected output and check matching the requirement. Various test cases were developed to cover all the necessary features of the blocks. The test cases were fired and the waveforms were analyzed to debug the RTL as well as test bench issues. All those issues were filed as bugs and resolved. Once all the test cases are passing, code coverage is done using a code coverage tool. The code coverage results are analyzed to uncover any dead code as well as logic which were never exercised. Few test cases are developed to fill the coverage holes to achieve 100% code coverage.