Effect Of Scaling On Two Stage CMOS Operational Amplifier with Different Scaling Laws

Abstract

Systematic reduction of overall dimensions of the MOSFET device as allowed by the available technology while preserving the long channel behavior is called as scaling and scaling laws are used as guides to MOSFET miniaturization. In modern literature six different scaling laws have been proposed. They are constant electric field (CE), constant voltage (CV), quasi constant voltage (QCV), constant dimension (CD) and quasi constant dimension (QCD1 and QCD2). The current work presents the effect of scaling on two stage CMOS operational amplifier with different scaling laws. The thesis is divided in two parts. The first part contains the effect of supply voltage reduction in two stage CMOS operational amplifier with different scaling laws. And the second part contains the effect of channel length reduction in two stage CMOS operational amplifier while keeping the same aspect ratio. From first part, it is found that CE and QCV scaling laws give the best performance of the six scaling laws. Optimum performance is obtained between 1.65V to 3.3V. CE and QCV scaling laws yield significant power saving while maintaining the voltage gain in the range of approximately 65-75 dB, bandwidth of approximately 10 KHz and unity gain frequency of approximately 50 MHz. Scaling is dependent on the process parameters that are oxide thickness (TOX) and substrate doping concentration (NSUB). The current work takes into consideration the scaling of only lateral dimensions (W, L) and supply voltage (VDD) using CE and QCV type. So for this we proposed one kind of arrangement according to which our circuitry work on two phases (1) 3.3V, W, L (2) 1.65V, W/2, L/2. This arrangement uses chip power sensor, indicator and switch module that detects the reduction of the supply voltage and according to which switch our circuit from design I to design II for maintaining the performance of the circuit at low supply voltage. The design is implemented with 0.7 μm and 1.4μm with a range of 1.65V to 3.3V as power supply. The scaling factor we have used here is S = 2. xvii To define second part we have coined one terminology called Scaling Factor (S). Scaling Factor means varying both channel length (L) and channel width (W) such that its aspect ratio (W/L) remains same. For example S = 10 means L = 3.5 μm and S = 1 means L = 0.35 μm. Here we are actually varying scaling factor from 1 to 10 and analyze its effect on all parameters of a two stage CMOS op-amp through graphs and then combine all graphs in a single graph. And then generate the equation for all graphs using curve fitting equations and then summarized it into one general formula that is applicable to all parameters of a two stage CMOS op-amp and also plot all graphs again which is doing comparison between simulated graph and graph through curve fitting equation. And finally make three layouts of a two stage CMOS op-amp at different scaling factor i.e., at S =1, S = 5 and S = 10. And then plot one more graph between layout area and scaling factor and then add this graph to a combined graph. After then we have done the comparison between pre-layout and post-layout simulation curve of all parameters of two stage CMOS op-amp with respect to scaling factor (S). The design is implemented in the range of 0.35μm to 3.5 μm with a 3.3V as power supply.