Analysis and Design of High Speed Low Offset Power Efficient Dynamic CMOS Comparator in 180nm Technology

Abstract

The Analog to Digital converters (ADCs) and Digital-to-Analog converters (DACs) are the key interface blocks between the continuous time domain and the discrete-time digital domain. They are found in an extensive range of devices in consumer electronics, medical equipment, communication and instrumentation applications, and current growing areas, and wearable devices etc. The basic building blocks of a ADCs and DACs consist of analog circuits such as voltage reference, operational amplifiers as well as mixed signal circuits such as comparators. Besides data converters, the comparator has many other applications such as memory, relaxation oscillators, null detector, zero-crossing detectors, peak detectors, switching power regulators, high-speed wireless and wireline communication systems, and many more. This has generated a enormous demand for high-speed low offset power efficient comparator that can be realized in a mainstream submicron CMOS technology. The ever increasing need of high speed, area efficient, high precision and power efficient analog-to-digital converter forces towards the exploration and usage of the dynamic comparator to optimize power, area and maximize the speed. In this research, a new flanged high-speed low offset power efficient voltage comparator architecture is introduced. The analysis and design of a high speed low offset power efficient dynamic CMOS comparator based on fully differential and double tail structure is presented. A novel concept of fully differential double tail dynamic comparator (FDDTDC) realized with high-speed, low offset with optimized power and area than that of the conventional dynamic comparators is proposed. The simulation is carried out using 180 nm CMOS technology with a supply voltage of ±0.9 V, at 1.3 GHz of frequency resulting into the delay of 0.37 ns while consuming 265.25 W of power. The proposed comparator has 1 mV accuracy and 10-bit resolution. The proposed comparator has lowest PDP and FOM, which are 8.59 fJ and 0.20 fJ/decision. The comparator has very much low offset voltage of 0.36 mV and higher common-mode voltage range. The proposed architecture demonstrates the drastic improvement in terms of delay, offset, PDP, FOM with optimum power and area as compared to the conventional comparators. The logical expressions are derived for delay, offset and power. With the help of logical expressions, the designer can obtain insight view of the different parameters, which are the main contributors of the offset voltage and delay in the dynamic comparator. Based on the investigations and findings, various trade-offs can be explored. Using Monte Carlo simulations, the effect of mismatch on offset voltage is studied. To test the process variation, all corners including supply voltage and temperature are analyzed for the proposed design along with reference comparator. The post layout results are also obtained in 180nm CMOS technology. Finally, all the obtained results are compared with state of art architecture in terms of performance parameters. The offset voltage, delay and power of the proposed comparator are about 91%, 45% and 30% less respectively in comparison to the state-of-the-art comparator, making it favorable for data conversion applications. The end result reveals the potential of new proposed comparator architecture and design methodology for high-speed low offset power efficient applications.