Simulation of Display Port Multi-Stream Transport in Intel's Display Pipeline

Abstract

For any computing device like laptop, tablet, mobile etc., the display of the device is the first element which the end-user notices. Thus display of the device, plays a major role in shaping the entire visual user experience. Providing a great visual user experience is one of the major aim for any company which is in the field of designing and producing computing devices. Intel being a major player in this field, has given special emphasis on enhancing this. A Graphics Processor on the computing device is responsible for driving the display which is connected to the device via a display link. Nowadays, display links are commonly seen in most of the display devices for establishing a connection between PCs to monitors, between a television and a set top box etc. Consumers usage and demand for higher resolutions has escalated rapidly in the past few years. DisplayPort (DP) is one of the powerful open link digital standard developed by Video Electronics Standard Association (VESA) to fulfill the consumer needs by providing higher resolutions through DP Tiled displays (image being divided and stored into two frame bufers in the memory), multiple displays connection to a single source output, high data rate, lower form factor etc. Multi-Stream Transport (MST) is a new technology introduced by VESA which is supported by DP versions greater than 1.2 that are capable of giving an output of two or more video streams having different properties which increase the produc- tivity of the device by 42%. The validation of the MST scenarios for DP requires a rigorous and lengthy process if executed manually pertaining to more cost, increased lab space for multiple panel connections and manpower. Automation is one such area which results in the reduction of time, effort and cost needed for the validation of such end-user scenarios. The process of automated validation of the Intel Graph- ics Driver is achieved through the simulation of DP MST in Intel's Graphics Display Pipeline by stubbing the DP panel details to the Graphics Driver through a Simu- lation Driver instead of connecting a real physical DP panel to the hardware. The Intel's Graphics development team has developed and designed a Simulation Driver that communicates with the Intel Graphics Driver and ultimately simulates the DP MST configuration and even the DP Single-Stream Transport (SST). Simulation Driver covers validation of 90% of the DP MST code in the Graphics Driver, can be configured to simulate any variety of DP MST hubs and displays (even without real panels/hubs) and thus helps in saving manual efforts (since most of the tests can be automated) and also helps to reduce bug escaping to OEMs (Original Equipment Manufacturer)/Customers. This thesis overviews the various methodologies carried out by Intel to validate the various DP end-user scenarios for various Intel platforms through Automation. It also explains about the implementation of the latest DP MST Simulation Driver. Various end-user test scenarios like hot plug or unplug of DP SST and MST configuration are developed and validated using DP MST Simulation Driver. These test scenarios were able to catch some real driver bugs, hence proving the efficiency or capability of this DP MST Simulation Framework. The test case development was made generic enough to be executed on the multiple Intel's Graphics platforms to provide easy maintainability and exibility.