Strategies & Methodology Addressing Low Power Design Challenges

Abstract

With the increase in portable devices and shrinking of technology nodes, power has become a major design criteria. At present both static and dynamic power dissipation are of major concerns and to overcome these, new techniques and standards are getting introduced .Design complexity has increased significantly and hence the use of EDA tools have become inevitable. Introduction of Unified Power Format and consolidation of power techniques in EDA tools has helped the designers to understand power architecture ,reduce power dissipation in design and compute pre-silicon power before the design is fabricated. This objective of the project is to address the challenges faced while implementing the methodologies related to power reduction used at different design levels and address those gaps by implementing them on reference design and ow ushing them through a predefined ASIC design ow. Lastly, Qualifying the power data and the collateral obtained is important before integrating an IP into a SOC which can be done by implementing quality checks on them. This task can be made simpler by creating automated power checks.