Methodology For Silicon Qualification Of Standard Cells: Design, Verification And Silicon Debug

Abstract

A new technology before being used in products has to be validated on silicon to check for various parameters like power consumption, manufacturing feasibility, electrical characteristics and PVT variations etc. Once it has been silicon qualified, it can then be used for mass production. Test chips, as the name suggests, are used to test these new technologies and IP cores like standard cell library, memory library, PLL, PMBs, etc. on silicon. Here, at ST, the testing architecture used to test the functionality of each cell of standard cell libraries is called ALLCELL. ALLCELL consists of a cell whose output is taken to a scan flop, called reference flops. Each standard cells output is taken into a scan flop, called reference cell, and they are stitched together. Cell output is also directly taken to a mux. The two outputs are compared to validate the functionality. In order to implement this methodology, complete RTL to GDS flow is employed. Design RTL is coded in Verilog and then using industry standard synthesis tools, the design is synthesized. The design is then functionally verified on CAD using simulation tools. These functional patterns are tested on silicon through the ATE. Post silicon results are analyzed through the debug setup environment.