Scan Analysis & Coverage Improvement forLeading ProcessTechnology

Abstract

Testing is very important aspect of any VLSI product. Compromise in testing directly affects trust of people on product and company. As SoCs are becoming more complex day by day DFT has very important role in the design. In fact, DFT is expanding as the technology is shrink- ing.Scan based testing of logic is primary coverage strategy used in modern design. Our goal is not only limited to high test coverage but also to reduce test vector development time and test application time. DFT related issues (like controllability of clock and reset , approximation of test coverage etc) need to be detected in early design stage, so that future scan insertion and ATPG activity can produce high test coverage with minimum iteration. For this purpose before scan stitching, an extra stage for RTL DFT checks has been added in design flow. After DFT RTL checks, ATPG is performed on synthesized netlist. ATPG coverage debug is performed in order to enhance the test coverage. Boarder sealing is enabled if partition level coverage is below targeted value. ATPG generated patterns need to be verified before design goes to silicon to identify issues like mismatch in RTL model and ATPG library, timing related issues like setup/hold time violation, issues with test setup etc. For this purpose Gate Level Simulation (GLS) is performed. Goal of performing all these activity is to generate test patterns to achieve high test coverage.