Timing Model Validation To Reduce Turn Around Time

Abstract

In the present time the chip complexity is very high, so designers go for the hierarchical design method instead of flat designing (i.e all the logic and whole SoC by same individual) and also the run-time if the designer goes for the flat designing is very high. In this scenario the best solution is to break the design in different blocks i.e partitions and work on the individually. The problem with this approach is when the designer tries to do the Timing closure of the SoC they get many interface violations which will create problems for them, other problems associated with the same is interface SlowSlope and Max Capacitance violations. The internal timing of the partition is taken care individually. The main problem that the designer faces is due to the IO constraints i.e the delay values that are assigned at the IO’s which play a major part in the timing closure. The aim of this work is to validate the Timing Models that are created from the Timing Tool flow and understand the problems which are associated and at the end try to replicate the model with overcoming that problems.