Logical Convergence of High Speed Design using Formal Verification

Abstract

Verification of SoC consumes about 70 percentage of the total turnaround time of design process. In this project the main focus area is to implement and verify high speed SoC(System on Chip), which will be working on data rate of 5Gbps. Also very new methodology i.e. PIP (Partition in partition) is being used in this project. So, this project presents a novel approach, which significantly reduces the formal equivalence verification challenges and also reduces the manual time spent by designers on debugging. This project also presents the power aware equivalence verification problems, which has become an important part of SoC design in evolving technology nodes. With emerging trends in extended RTL modeling and shrinking time-lines, design team needs to adopt robust FEV(Formal Equivalence Verification) methodologies leaving no gaps in verification process to ensure quality. These methodology enhancements and automated paranoia infrastructure to converge functional and power aware FEV are addressed in this project. In precise, FEV is one of the key activities in SOC design cycle and is a key convergence to ensure correct implementation of VLSI designs, by verifying the equivalence between the implementation and specification (RTL or gate) along with the low power implementation. Another key objective of this project is ECO (Engineering Change Order), which is one of the crucial stage of product design cycle. In very less time, designers need to take care of such engineering change orders. Criteria for successful ECOs is that not only functionality but also timing and congestion need to be taken care of. This project discusses basics of ECO, some of the challenges and flow of Conformal ECO tool flow. The deliverable of this project is to verify High speed SoC using formal verification. PIP methodology is been used to verify blocks and debug non equivalents. Also successful ECO is generated at very crucial stage of Project.