Optimal Methodology for Signal Integrity based Timing and Noise Analysis of IP’s and IP Interface Modeling

Abstract

Scaling of device dimensions into the nanometer process technology has led to a reduction in the gate delay. However, delays across interconnect have not scaled in comparison to gate delays. Also, due to process-technology scaling, the spacing between adjacent interconnect wires keeps on shrinking, which leads to an increase in the amount of coupling capacitance between interconnect wires. In the early years, the impact of coupling noise on chip level signals has become a major source of static timing errors. Cross Coupling noise has become a major issue which must be consider while performing timing verification for VLSI chips. The main reason for coupling is crosstalk. Crosstalk can result in significant delay variations as well as noise variation of signal integrity issues in modern day CMOS circuit design, minimizing the noise and the delay analysis due to crosstalk in data propagation have much greatest interesting in the research sector. A major component of noise and delay analysis due to crosstalk in processors is the transmission of data through high capacitance system-level buses. Crosstalk induced delay and noise analysis have become a major determinant of the system performance. Avoidance of crosstalk can greatly boost the system performance. In this project, find an optimal methodology that how PrimeTime SI performs crosstalk analysis for any given IP and IP interface with regular PrimeTime analysis flow. What all are the factors effecting Signal Integrity and Noise Analysis will be listed. ETM (Extracted Timing Model) is abstract representation of block which is used in place of block netlist for timing analysis at a higher level of the design hierarchy. Here validation of ETM models which is verification of ETM generation, compares timing of original netlist and ETM timing by comparing each path slack or each I/O timing arc delay.