At-Speed ATPG Aware Scan Stitching

Abstract

With today’s design size in millions of gates and working frequencies in gigahertz range, testing has become an important and an integral part of the VLSI design flow. Metrics like Fault Coverage have become one of the important parameter to be considered while designing a chip. Complex and efficient machines like the ATPG and ATE are developed to reduce the time and efforts required in testing. Many fault models are developed to represent the physical defects. Though the traditional Stuck-at faults cover most of the defects, defects like high impedance metal, high impedance shorts, and crosstalk are not caught by traditional stuck at scan vectors. They are only detected by Transition fault model which is tested by At-Speed testing. Also with the decreasing transistor size, the number of these defects tends to increase. Hence At-Speed testing plays a crucial role in testing of modern day chips. The test inputs to a chip are applied by using a Scan Chain in which the flip-flops are stitched to form a continuous chain. Most of current algorithms does the stitching to reduce the wire length of the inserted scan chain i.e. physical aware stitching. In this project, efforts are made to stitch the scan chain in such a way that it improves the at-speed coverage and also try to reduce the test patterns required for testing the chip.