FPGA Based CCD Timing Generator

Abstract

The Charge Coupled Device (CCD) is a major piece of technology in digital imaging. It is used in imaging satellites for different types of applications like earth observations, minerals mapping, cartography, space astronomy etc. As compare to CMOS Detectors, It provides lower noise and higher dynamic range. There are different types of CCD architectures and each requires a Timing Generator to operate it. The signals required by the CCDs are not a fixed frequency clocks that is why it cannot be generated using crystal based clock generators. The clocks frequency is also dependent of Variable Integration Time (VIT) settings. So, a Programmable Timing Generator required for generating clocks for different VIT values. A CCD Timing Generator with fixed integration time, a Programmable Timing Generator with variable integration time and its various components are designed simulated in Libero SoC v11.2 using Verilog Hardware Description Language (Verilog HDL). The design is targeted to A3P250-VQ100M Microsemi FPGA. A programmable interface is developed to supply value of Integration Time using micro controller to Timing Generator.