Improvisation & Deployment of Methodologies to Have Productivity Gain in Characterization and Design Verification flow of Static Memories

Abstract

Memories are leading semiconductor component which occupy around 70-80% area on a typical SoC store digital information in massive quantity, hence are essential subsystem in modern integrated circuits. The ever-increasing demand for low priced memories with low power consumption, high performance, high density and small package size has compelled the fabrication technology and memory development towards more compact design rules and consequently towards higher data storage densities. Advanced technology nodes enable the designers to integrate more functionality but this integration comes at a cost. Hence nanometer process designers are facing many challenges, which may cause negative impact on product yield and time-to-market constraint. The main motive of my project is the improvement in methodology to mitigate the challenges faced in post layout characterization and design verification flow in advanced technology nodes for a full custom SRAM memory design. Characterization of memory means to get information about its behaviour in terms of different timing, power, leakage, capacitances and marginalities. This helps in evaluating the performance of memory and improves upon the design. When a set of specified inputs is applied to the memory it includes running simulation on post layout netlist and then doing measurement from the simulated values. We can bucket post layout challenges into two main categories: Extraction related and Simulation related. Characterization to be done with good accuracy and reasonable run-time. Characterization is done with help of simulations at circuit level. Two types of simulators available: True SPICE - Golden (equation based) and Fast SPICE (Optimization based upon algorithms). With True SPICE simulator, high accuracy is obtained - equation based. With Fast SPICE, significant reduction in run-time - accuracy compromise. Also fast SPICE have some optimization options with which trade-off can be done between accuracy and run-time. Enabling relevant algorithm in fast SPICE for design is important in order to have reasonable accuracy and runtime. Also improvement of existing characterization methodology to make it more efficient.