Critical Path Sensor

Abstract

In lower technology node, to predict an exact delay is a bit difficult because of different types of on chip variations. These on chip variations occur due to mask alignment, etching process etc. We need to keep some margin in which delay can be changed. If this margin is very high, then it is difficult to achieve targeted frequency and if the margin is very low then it may cause function failure. This margin is called as De-Rate Factor. Generally Derate factor is a constant which is given by signoff team. Derate Factor can accurately be known by considering different types of variations. The circuit is made such that we can detect effect of both systematic and random variations so that we can get Derate factor considering all types of variations. Characterization is a process to get exact delay from one flop to another flop. Here both clock path and data path needs to be characterized so as to get exact delay when intentionally we fail setup or hold so that we come to know by what factor delay changed on various PVT corners. In the real design critical paths, when intentionally setup is failed, characterization of data path as well as clock paths is necessary. Setup and hold time of flops also plays an important role in chip designing as we must handle setup and hold violations to meet timing requirements. In this project, with the reference of previous available data, the design to find Derate factor is modified to get more accurate result. Gradually increasing frequency in design will fail the setup and at that time we will compare the clock and data path delay on both CAD and Si, which will help to see effect of process variations.