Enablement of High Voltage DRC and Fill Flow for Cadence Platform

Abstract

With advancement in technology node, circuit complexity is increasing rapidly. Hence, "Design For..." are not optional part in IC design anymore. They have become unavoidable part of design flows. Nowadays, it is common to have different voltage domain designs manufactured on a single die. Probability of two different voltage domain nets placed close to each other is very high. This potential difference can create an electric field which can affect sensitive area of design and causes reliability issues for circuit. Hence, High Voltage DRC checks are important part of design flow to prevent reliability issues due to electric field. Though, circuit is perfectly designed for its functionality, if not manufactured correctly may result in failed design. Manufacturing quality directly affects circuit performance and yield. Fill comes under Design for Manufacturability. Without Fill circuit can not be even manufactured as after chemical mechanical polishing if feature density is not as per criteria, lithography can not be carried out successfully. This makes Fill an mandatory design step requited to be followed before fabrication. This project comprises development of High Voltage DRC rules and Fill flow for different layers. Both are implemented in Cadence Platform. High Voltage DRC checks provides reliability assurance of circuit while Fill reduces failure probability of design when manufactured. Development of both flows will be followed by test case generation to validate and qualify the project.