Performance Verification of Bus Interconnect

Abstract

Bus interconnect is an important logic, which is used to communicate between two IP block units in SOC. It becomes complex with advanced SOCs. Also it needs to calculate time required to transfer transaction from one block to another block, number of data bytes transfer in each transaction. The Functional Verification checks the functionality of the blocks. Timing related information cannot be determined by the Functional Verification. Therefore along with Functional Verification, Performance Verification of the SOC interconnect is required. Performance Verification is very important approach for checking the efficiency, speed of the design. In the Performance Verification, performance parameters - bandwidth and latency are calculated for different paths and measured actual values are compared with expected one. Various approaches are developed for verifying the performance of the interconnect; one of the approach is to develop configurable / reusable component Performance Monitor. First the Performance Monitor is configured according to the configuration table provided by the user. Then it is integrated with the design or IP block. The timing critical paths are determined on which latency and bandwidth are going to be calculated. It measures per transaction latency, average latency and average bandwidth and generates report.