Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/8585
Title: Impact Of Reset Domain Crossing On PowerPro Tool
Authors: Modi, Ritika
Keywords: EC 2015
Project Report
Project Report 2015
EC Project Report
EC (VLSI)
VLSI
VLSI 2015
15MEC
15MECV
15MECV20
Issue Date: 1-Jun-2017
Publisher: Institute of Technology
Series/Report no.: 15MECV20;
Abstract: Power consumption is one of the top concerns of Very Large Scale Integration (VLSI)circuit design, for which Complementary Metal Oxide Semiconductor (CMOS) is the primary technology. Today’s focus on low power is not only because of the recent growing demands of mobile applications. Even before the mobile era, power consumption has been a fundamental problem. To solve the power dissipation problem, many researchers have proposed different ideas from the device level to the architectural level and above. However, there is no universal way to avoid tradeoffs between power, delay and area, and thus designers are required to choose appropriate techniques that satisfy application and product needs. In general, low power VLSI Design can be achieved at all levels of the VLSI Design (system, algorithm, architecture, circuit, logic, device, technology levels). But optimizations for low power VLSI Design done at higher abstraction results in comparatively higher power savings. The tool used for power optimization also effects some other parameters, if not taken care may lead to metastability. During Power Optimization technique, some factors needs to be taken care, like metastability , so that expected result does not vary. Metastability effects the output of design , Thus some factors like clock domain crossing & reset domain crossing should be considered. synchronizers when used removes the metastability due to clock domain crossing . Similarly Reset Domain crossing also leads to metastability when source flop is asserted with reset while destination flop does not have reset assertion at the same time. Those scenarios needs to be worked on , where reset domain crossing condition is added by PowerPro tool in clock gating or reset hierarchies.At the end, flow was automated to run with multiple designs so as to error out when differences in orig RTL and power optimized RTL was observed .Flow for Reset Domain Crossing violation, analysis, challenges & results observed are mentioned in this report.
URI: http://10.1.7.192:80/jspui/handle/123456789/8585
Appears in Collections:Dissertation, EC (VLSI)

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