Designing and Verification of IPs

Abstract

The key focus of the IC design industry is to deliver first pass IPs. This becomes extremely difficult due to increase in the complexity of the modern circuit designs, as finding bugs in the IPs is very challenging. Thus verification has become the bot- tleneck of the entire design process. Therefore, there is need for a practical solution to reduce the verification time. Verification consume much of the SOC design efforts. Fierce product competition in system features and capabilities drives demand for advanced silicon designs. The SOC design gap widens every year. To reduce the time to market one needs to min- imize the verification time. Hence, different methodologies are used to verification. Verification is done at IP level and at SOC level. At IP level the IP is verified for re- usability and configurability. Considering these key points VIP for the DPI(Display Pixel Protocol) interface was developed. At the SOC level the key features to be verified are the reusability of the test- bench, interconnections between the IPs. To verify the interconnections between the IPs various protocols are used. One such protocol is AXI3 protocol. Using these standard protocols reduce the design time to market. The Watch Dog Timer is an integral part of all the SOCs. Verification of such an IP at the SOC level is im- portant. The development of verification environment for the IPs at the SOC level should be independent of the processor. This will enable reuse of the environment for the particular IP across different projects.