Analysis & Design of Linear Voltage Regulator for DDR I/O application

Abstract

The Linear Voltage regulators are widely used in present portable electronics industry and important part of the power management unit. Now a days we try to integrate more and more block in SoC , because of that supply voltage become a poor quality.So we need stable supply voltage irrespective of load variation, temperature. So Linear voltage regulator is used to protect the sensitive analog blocks from Coupled supply noise. In this thesis , Linear voltage regulator design for I/O application where output voltage changes suddenly. This linear voltage regulator provide high and current so that stability of linear voltage regulator become a complicated. Frequency compensation scheme is used to make system stable for different load current and different load capacitor value. Efficiency of regulator is depends upon quiescent current so that proposed linear voltage regulator work in two different mode which are high power and low power mode where quiescent currents are different. Power mos is pMOS because drop across pMOS is very less compare to other type of transistor. Inrush current will decide start up time of linear voltage regulator. In this proposed linear voltage regulator by splitting power transistor we can control inrush current. Load and Line regulation is define the transient variation in output voltage when load current and supply voltage are varying. Load and line regulation are improved by increasing open loop gain and bandwidth. Linear voltage regulator is design in UMC 40nm technology.Simulation results confirm a PSRR of -37 dB till 10KHz for the maximum load current of 160mA. The load and line regulation transient variation is less than 50 mV. Inrush current value is less than 100mA and start up time is around 345μs.