Efficient Physical Design Methodology & Convergence of Server SoCs Partitions

Abstract

In the process of ASIC manufacturing, the main aspect that remains after logic and circuit design is Physical design of the chip which basically covers floor planning, placement and routing in the lead. Considering the fact of increasing complexity in the physical design methodologies due to changing technology nodes and to compete with the rapidity of the changing market, the conventional methodology of physical design is inefficient at many points. Hence, an efficient methodology or more than one methodology is required to meet the design requirements promptly and accurately. The aim of this project is to propose an efficient physical design methodology which focuses on better placement and routing techniques, Timing to meet the desired specifications which will help to converge the design into quality product with the help of tools like Design Compiler, IC Compiler II, Prime Time, and Conformal LEC.