Optimum Methodology for Synthesis, Placement & Routing of Mix Signal IP’s & It’s Implementation

Abstract

This Project is mainly focused towards backend domain of VLSI like Synthesis, PnR and Timing Closure, but before we proceed we should be able to understand both flows as well as tools that we can use to implement them. This report contains flow steps that synthesis and APR contains and detailed description of them. DC compiler and IC Compiler are widely used tools to implement synthesis and APR respectively, this thesis contains basic information for DC as well as ICC also. As we proceed towards optimum methodology we need to understand the reports and outputs generated by tool, algorithms used by the tool to get optimum result. We know PrimeTime is the best timing sign off tool. So whatever results we are getting from ICC to make them more realistics we need to compare them with PT results and need to check whether it is same or different and the parameters affecting timings which leads to miscorrelation in final results. PrimeTime uses AOCVM model for timing calcultions while ICC uses flat derates and gives results in shorter time compare to PrimeTime. CCS and NLDM are two main timing models that every industry use for timing. I have tried to compare each case for each models and their compansated derates. Here I have included results related to each and every case like ICC-CCS with default derate, ICC-CCS with reduced derate etc. I have included comparison graphs for Endpoint delay(arrival time), Slack and Depth vs Slack Difference histogram. Every industry need to do this kind of timing analysis for the betterment of timing results. As both PT and ICC are used in industry so which is better in what case somehow we can make them correlated then it will be better to reduce product cycle and human efforts that is required for industry. Thesis contains basic ECO methods. ECO means engineering change order. When design is already ready but still some changes is required to fix violations without affecting basic design, ECOs can help. In ECO process we generally try to remove violations to meet the specification of design and better performance of design. In both tasks we need to have basic understanding of Synthesis, PnR and Timing Closure. This thesis contains all basic information require related to them.