Automation of AVR Test Benches using VAMPIRE Tool

Abstract

Modern power management System on Chip (SoC) design demands for fully integrated solutions in order to decrease certain costly features such as the total chip area and the power consumption while maintaining or increasing transient response to signal variations. Low-Dropout (LDO) voltage regulators, as power management devices, must comply with these recent technological and industrial trends. The thesis focuses on two different work which comprises of Validation of different LDO Architectures and Enhancement of Intel Corporation specific tool. The objective of the thesis is to understand tool, learn Low Dropout (LDO) Regulator, carry out different analysis to validate different test-benches using tool, to check reliability of device and to enhance the tool capability. In order to validate test benches, different types of analysis are understood and required data is carried out. The purpose of using this tool is to reduce the efforts and time required to carry out validation of Analog Design. Different analysis are carried out with the help of tool. The tool is capable of regression testing with less efforts but flow of the tool was not smooth and few features to reduce efforts and improve timing were missing. Tool enhancement and addition of few features in the tool are carried out using Perl scripts. The thesis also covers different impacts on the design when model library is updated and parameters required to be corrected to overcome it.