Mixed Signal Implementation in Advanced Node for Cadence Platform

Abstract

Most SoCs currently being developed have various functional blocks which are Digital/Analog and Mix-Signal block. Typical design environments in past took care of analog and digital design methods separately, the design practices were focused on nature and function of designs, hence the design flows and design tools also developed in same way. With increased requirement of mixed signal circuitry new methods/flows were required designer to take care of them. Initially new set of mini flows/methods and tools were evolved to bridge Analog and Digital design flow/methods. But this involved translation of design data (which respective design environment can read/understand) multiple of times and analysis methods involved approximations. While translation remained only way to bridge analog and digital world, it involved a great deal of design time, and with design capacity increased the design time involved in translation also increased and approximations lessen the accuracy of analysis. Hence it was required to have common design database which both analog and digital design world can understand. Open Access (OA) database was an answer to this problem, OA database is understood by both analog and digital design environments such as Virtuoso and Innovus. Open Access not only supported various design objects used in both digital and analog environments but also allowed user to ripe benefits of various design features which both design environments provide. The benefits comes from these interoperability flow is not only about saving design data translation time but also the benefits involved with respect to aide it provide in various design tasks. In this project, using LEF, DEF and GDSII files the complete ASIC flow is developed and carried out.Then the same flow is carried out using one common database OA(Open Access) which is developed taking reference of LEF file. Timing analysis of both the flow is done and comparison is done. Workarounds were created for tool issues and missing functionality in native tools. This includes ITDB (Integrated Technology Database) based OA techfile generations was done which is major task. It is flexible to convert any general techfile to ITDB based OA techfile which is helpful to interoperability. Another major workaround is additional ICV runset based Auto Via Insertion procedure which automatically inserts vias at the required missing locations to generate connectivity information and improve reliability of the design.