Power and Performance Analysis of Mobile Based Chips

Abstract

The real motivation comes from Moore’s Law which explains that how so many transistors can be embedded into a single chip. This forms the basis the how the power is supplied to each and every port with minimum leakage and maximum usage of device thus increase in device life. Understanding the topic itself is a part of literature survey because this covers all the aspects of power in correlation with the VLSI design flow. Power and performance go hand in hand as both are the counterpart of each other and need to be monitored for better functioning of the device and increase the device life. The further discussion touches the important aspects of leakage power and its connection with the design process, the gating aspects and the effect of gating on the device is an interesting topic for which an entire chapter has been dedicated. Validation plays an important role in the designing because the concept of validation itself is to make the balance and verify the power. It also enables us to check an equilibrium between the available results because validation saves a lot of time and it is an important process to find bugs and rectify in advance rather than when the silicon is available to us all this will help to understand the designing and testing part of the chips with power as the main point of consideration. With the onset of the consumer era there are various mobile applications available which are popular among the consumers. As an outcome of which power optimization is important now a days. Designers do several iterations to optimize power in order to achieve their power budgets. Though power should be optimized at all stages of the design flow, optimization in early design stages have the greatest impact in reducing power. The discussion in the thesis continues with result where we have 2000 + signals out of which we will be only discussing the G1 signal based upon which our whole analysis and simulations are carried out.