Efficient Physical Design Methodology & Convergence of SOC Partitions

Abstract

In the process of ASIC manufacturing, the main aspect is Physical design which basically covers floor planning, placement and routing in the chip. Considering the fact of increasing complexity in the physical design methodologies due to changing technology nodes and to compete with the rapidity of the changing market, the conventional methodology of physical design is inefficient at many points such as timing optimizations, floorplan , placement. Hence, an efficient methodology or more than one methodology is required to meet the design requirements accurately. There are many aspects to make conventional physical design methodology to efficient, in this project we are going to cover few aspects such as better floor planning Placement of the SoC partitions by improving sanity checks at early stages of the flow. This sanity checks ensure that the guidelines are properly followed. This also includes proper power planning in the Design which will make sure that all cells in the design are getting connected to power network properly. To meet the required timing specifications of the SoC Partitions, on the top of conventional methods by including some additional methods like group path, creation of bounds, ideal nets, Design compiler will do better timing optimization at the synthesis level only so that 80% of the timing requirements can be archived in synthesis only and rest 20% can be taken care by placement & Floorplan. By adding above methods in the conventional flow, Runtime can be reduced as compared with conventional methodology. Number of iterations to converge the design also will be reduced. Timing results can be improved compared to the conventional methodology. This all methods can be implemented with the help of Synopsys tools such as design compiler, IC Compiler, Primetime.