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http://10.1.7.192:80/jspui/handle/123456789/8839
Title: | Validation Tool Development for Memory Reference Code |
Authors: | Rana, Pallav |
Keywords: | EC 2016 Project Report Project Report 2016 EC Project Report EC (ES) Embedded Systems Embedded Systems 2016 16MEC 16MECE 15MECE19 |
Issue Date: | 1-Jun-2018 |
Publisher: | Institute of Technology |
Series/Report no.: | 15MECE19; |
Abstract: | In the process of computing system booting, DRAM controller and PHY inter- face initialization is very crucial task. Since the Dynamic Random Access Mem- ory (DRAM) is used as main memory during run-time and also it is used to store firmware data during boot-time, the improper initialization of RAM may lead to critical breakdown of platform. The firmware which manages the Memory Con- troller (MC) initialization, PHY initialization and the commands for memory train- ings for DRAM in the Intel Platforms is known as Memory Reference Code (MRC). MRC is handles memory controller initialization, read/write timings and voltage op- eration for optimal memory performance. MRC performs read/write leveling, Vref tuning, command/address/control signal training operations in order to bring up the memory as efficient way as possible. The MRC developers focuses their work mainly on MC and PHY registers initializa- tion. The design team from Intel provides the list of registers for memory controller and PHY initialization. The MRC developers gets values for registers from the sheet given by design team.This sheet contains values to be configured in large number of registers according to memory operation frequency, operation gears and the se- quences to be followed. The MRC code writes thousands of registers in MC and PHY modules. Keeping track of all the values initialized according to different operating parameters is highly difficult and it takes lots of debugging and long turn-around time for all the people involved. It has to be made sure, that each register is con- figured with value given by design team. The tool here developed helps wide range of engineers in providing confidence about the MRC execution. The MRC Checker tool runs on a host computer which is connected to board under test through Lauterbach debugger. It fetches the platform register values with the use of PythonSV commands and compares it with design team's spreadsheet values. The final output is generated with the mismatch displaying the register values. This report discusses the design, development and results of a tool known as MRC Checker tool. The aim of the Checker tool is to validate the memory reference code by checking the register values in MRC execution. The tool will give confidence to MRC developers and Power ON (PO) engineers regarding their code development and also it will help to figure out and solve the issue related to MRC. The MRC Checker tool plays an important role in helping BIOS developers,MRC developers, PO team, validation engineers, RTL designers etc. |
URI: | http://10.1.7.192:80/jspui/handle/123456789/8839 |
Appears in Collections: | Dissertation, EC (ES) |
Files in This Item:
File | Description | Size | Format | |
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15MECE19.pdf | 15MECE19 | 2.58 MB | Adobe PDF | ![]() View/Open |
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