Designing and Timing Analysis of Decision Feedback Equalizer in Receiver

Abstract

The growth of Information processed by integrating circuits demands that data be transmitted through channels at multiple gigabits-per-second. The limited bandwidth of channels caused by the rising resistive and dielectric loss of the channels at high frequencies gives rise to along channel impulse response or equivalently frequency-dependent attenuation. Inter-Symbol Interference (ISI) is the main concerned factor arising from channel imperfections with limited bandwidth. To mitigate this, usually, equalizers are placed in series with the transmitter to estimate the inverse transfer function of the channel. The performance of linear equalizer gets severely degraded for channels with very high amplitude distortion. Since the linear equalizer reproduces the channel inverse transfer function, to compensate for high attenuation in certain frequency bands, it is compelled to generate high gains in the same frequency bands leading to amplication of noise along with the transmitted signal. Also, linear equalizer only removes pre-cursor effects. Generally, in Data symbols, post-cursors effect are signicantly larger than that of the precursors. To overcome this issue, a Decision Feedback Equalizer which uses feedback of detected symbols to produce an estimate of the channel output is employed. Typically, the DFE is fed with detected symbols and it produces an output which is subtracted from the output of the linear equalizer to allow faithful recovery of the transmitted signal. Also, it removes post-cursor effects without attenuation degradation. In the present work, Main focus on its timing analysis to ensure that the chip meets all the necessary constraints to operate at the intended clock rate. The special emphasis on CML to CMOS block to get minimum jitter and noise requirements. Also, Phase interpolator design to increase its IQ delay range is presented here.