Improvements in PHY Timing Analysis Methodology to Achieve High Turn Around Time and Better Quality

Abstract

Timing in any design is crucial part, which includes setup and hold time analysis. It depends on many factors like cell and net delay, variation in cell and net delay. Also, to meet the target frequency, timing has to be met. On-Chip Variation is now another aspect which is dominating at lower technology nodes, making timing very difficult to meet. So, it is required to understand and replicate the actual operating condition in tool, which will be there on silicon. That operating condition may change due to process or temperature variation. After that, timing has to be fixed to allow the data to flow smoothly. In doing this, different methodologies need to be developed as process node changes. Here, the impact of different aspects of variation, i.e., Advanced and Parametric onchip variation have been analyzed, found that later is pessimistic in behavior, meaning providing more realistic scenario for variation. Depending upon the amount of variation predicted, derate (scaling factor for delay) has to be applied on cell and net to correctly analyze the design for timing. Net derate has been estimated to analyze the effect of variation on nets. Design also contains sequential elements like latch, so, latch behavior has been implemented on STA tool and different cases have been analyzed for timing. Engineering change order has been implemented to fix the violation, i.e., hold, setup violations, leakage power recovery. Again different combination of fixing order has been analyzed. Along with this, there is a need to validate the tool and tool-flows to achieve better qor as methodology changes. So, different quality assurance checks have been performed including validation of linking of standard cells from libraries, linking of macro cells and timing constraints, cell and net delay numbers, derate values on cell and net, RC parasitic annotation etc.