Deploying and Improving Clock Domain Crossing Verification Techniques for SoCs

Abstract

The Moore`s law has been motivating the semiconductor industries for complex mul- tiple clocks (mostly unrelated) SoC designs. Data/Signals that crosses such unrelated or asynchronous clock domains are more likely to be sampled before they are stable and can cause issues like metastability, etc. which may lead to respin. Such CDC signals must by synchronized between the domains using a valid synchronizer and must be verified in some way before quality sign-off. Thus, SoC designs with End user logic and Complex Subsystems and IP integration has multidimensional challenges. The typical challenge in at netlist based CDC verification checks is huge run time, memory consumption & million violation counts. Debugging and reporting violations inside IP & to migrate IP waivers at SoC level is a cumbersome, painful & time consuming process. This majorly affects project schedule and quality. These project used the SS and IP CDC abstracts models generated during IP CDC verification while doing SoC/top level CDC checks. This abstract model was treated as a Black-box and had complete information about I/O port level clock definitions & their relationships (sync/async) which is major re- quirement at SoC-level CDC verification. Run time and memory consumption is high at SoC level, but with abstracts one can manage the memory in better manner. Initial SoC CDC setup runs saw a huge memory peak but later when clocks, resets were defined properly at top the memory requirement dropped down. During intial analysis SSs and IPs abstracts were defined at top but then partitions were defined, which included mul- tiple SSs/IPs together in a single partition and then generated abstracts for respective partitions which was consumed at the final SoC runs. This helped in progressing and enabling to improve the CDC Verification for SoC in terms of memory consumption & time taken for sign-off.