Read/write Assist: Analysis of The Data Stability Across High Desnsity Sram Cells in Lower Voltage

Abstract

The Voltage scaling is required to minimize power consumption but in lower technology node the noise margin degrade with voltage scaling as a result improving the Noise margin is one of the important challenge in every state of the art SRAM design. Due to the Process variations like threshold voltage variations, supply voltage variations etc in scaled technologies, stable operation of the bit cell is critical to obtain with high yield in low-voltage SRAM and the low voltage impede read/write in static random access memories (SRAMs).In addition to that the condition is worsened when the periphery voltage is kept lower than the array voltage. To mitigate the above mentioned challenges the designers makes the use of assist techniques at lower power levels to design SRAMs. In this project the assist techniques (Read assist and write assist) are explained to enhance the read and write margins of the 6T SRAM bit cell and the same write assist circuit is applicable to enhance the write margin of the 8T SRAM bit cell. The simulations are performed in 28nm process Technology node and the read and write margin simulation results are compared with different SRAM circuits like 6T SRAM bit cell with cell ratio of 111 122 123 and Dynamic word line swing technique and 8T SRAM bit cell. The effect of temperature and threshold voltage values on Read and Write margins are observed. By using assist techniques, the read and write margins are improved.