Modeling and Optimization Techniques for Yield-Aware SRAM Pre-Silicon Tuning

Abstract

Today’s mobile devices, SoC or any smart electronic device demand large memories with stringent power and speed constraints. Cutting-edge process nodes (16nm,12nm,10nm,7nm) are needed to meet target bit densities; but these nodes have extreme statistical process variation, hurting yield on these high-volume chips. To design for yield, one must be able to measure it in the design phase. This in turn requires estimation of Bitcell and sense amp yields, for which a simple Monte Carlo approach would need billions of simulations. As size of SRAM is getting smaller, so it is particularly valuable to parametric failure, which reduces yield. The problem in SRAM is that there is clash between stability during read operation and ability during write operation, as we optimize the array Bitcell for read stability, write ability degrades. So my work represents the techniques which increases the performance of read and write operation of SRAM. Timing optimization for every memory instance generated from memory compiler using self-timing circuit. In the initial phase of the memory compiler development, various kind of analysis is done on the models provided by the foundry to decide the behaviour of the models in terms of timing, power, and leakage. Bit cell and logic are the two kinds of models which foundry provide for memory design. Bit cell design is provided by foundry and memory designers can do very small changes in the Bit cell design. Most of the effort in the memory design is in the periphery design which is made up of logic models and this is the main reason to do the logic model analysis. My work represents the analyse various margins like read margin, write margin, logic margin. Also all margins in aging PVT.