PCIe Physical Layer Verification using SystemVerilog & UVM

Abstract

Design reuse and verification reuse are important to satisfy time to market require- ments. Reuse of verification environment across different designs of the domain im- proves the verification efficiency. In this project single port RAM and PCIe Physical Layer verify using SystemVerilog and Universal Verification Methodology. Memory is used to read and writes data on particular location and it is also used for storage purpose. Different types of memory used for storage purpose. SystemVerilog language is particularly used to verify the design. It's known as industry-first Hardware De- scription and Verification Language. It combines the features of Hardware Description Languages such as Verilog and VHDL. Universal Verification Methodology is also used to verify both simple as well as complex digital logic design. It is used to reduce the verification time and complexity of the design. PCI Express is high performance, general purpose I/O interconnect communication protocol for various peripheral. PCI Express is third generation Computer bus to interconnect peripherals in a computer, servers, video game card, and motherboard. It is layered based, packet approach serial bus protocol. The data rate of PCI Express Gen1 is 2.5 GT/s and Gen2 is 5 GT/s. It has three different layers such as a Transaction Layer, data Link Layer and Physical Layer. The basic objective of this project is to verifying the LTSSM State of Physical Layer of PCI Express using SystemVerilog and Universal Verification Methodology. The PCI Express establishes many important tasks such as link width negotiation, link data rate negotiation, bit lock per lane, symbol lock/block alignment per lane etc. All this function is accomplished by Link Training and Status State Machine (LTSSM).