Building Testchip for Enabling Faster SoC Flow

Abstract

Verification of SoC designs plays a major role to check the product quality before it goes to market. While advanced Pre-Si Verification techniques can catch design bugs, it can miss physical bugs which can only be identified by Post-Si validation.The bugs found at later stage can increase the time for SoC design flow. To reduce the time to market and give left shift to SoC flow, Testchip methodology is used. This methodology tests the IPs which are going to be used in the SoC on new technology node. Post-Si Validation and Power-on sequences for such IP’s can be done prior to the first silicon stepping for the product SoC. This methodology uses the multi-product shuttle cycle to reduce the Post-Si Validation efforts for the corresponding SoC and reduces the time to market and give more silicon-confident IP. This thesis outlines the architecture of the Testchip and its Design Flow and how the Testchip is built to check behavior of IP with the different technology on die.The thesis will focus more on the various approaches used for Pre-Silicon verification strategy for the IP container based Testchip Design, Testbench Environment and Implementation of the same.